Flash memory has become increasingly popular in recent years. A typical flash memory comprises a memory array having a large number of flash memory cells arranged in blocks. One of the most commonly known flash memories is the one-transistor flash memory, wherein each of the memory cells is fabricated as a field-effect transistor having a control gate and a floating gate. The floating gate is capable of holding charges and is separated from source and drain regions contained in a substrate by a layer of thin oxide (tunneling oxide). Each of the memory cells can be electrically charged by injecting electrons from the drain region through the tunneling oxide layer onto the floating gate. The charges can be removed from the floating gate by tunneling the electrons to the substrate through the tunneling oxide layer during an erase operation. Thus the data in a memory cell is determined by the presence or absence of charges in the floating gate.
It is highly desirable to scale down write/erase voltages of flash memory. This has typically been achieved by decreasing the thickness of the tunneling oxide layer. However, conventional one-transistor flash memory has a conductive storage layer, and thus thin tunneling oxide layers will cause a significant leakage problem. Stored charges are more likely to be leaked to the substrate through a thin tunneling oxide layer than through a thick tunneling oxide layer. Particularly, if there is a defect in the tunneling oxide layer, all stored charges can potentially leak through the defect since charges can flow freely in the floating gate.
One method for reducing the thickness of the tunneling oxide layer without causing severe charge loss is using a (poly-)Si—SiO2—SiN—SiO2—Si (SONOS) structure. FIG. 1 illustrates a conventional SONOS flash memory cell. A tunneling oxide layer 2 is formed on a silicon substrate 3. A silicon nitride layer (floating gate) 4 is located on tunneling oxide layer 2. Silicon nitride layer 4 comprises local traps for trapping and storing charges representing digital data “1” or “0.” A blocking oxide 6 is formed on floating gate 4 to prevent charges from reaching gate electrode 8, which is typically formed of polysilicon.
In SONOS memory cells, charges are stored inside the discrete and electrically isolated traps of nitride (SiN), while only the trapped charges close to the oxide defects can leak out. Therefore, it is possible to store more than one bit in the silicon nitride layer 4. For example, by connecting the source region to ground and connecting the drain region to a high voltage, charges can be stored in region 10, which is on the right side of the illustrated structure. Conversely, by connecting the drain region to ground and connecting the source region to a high voltage, charges can be stored in region 12, which is on the left side of the illustrated structure. Furthermore, methods and structures for four-bit storage are being explored, wherein each side is used for storing two bits.
The existing flash memory cells, however, cannot save more than four bits per cell. Additionally, the conventional SONOS memory devices using silicon nitride as storage layers have the disadvantage of high conduction band discontinuity (ΔEC) with a silicon channel. As a result, charge leakage is still a problem and data retention time is adversely affected. To overcome these problems, relatively thick oxides are typically needed. However, thick oxides will cause an increase in write/erase voltages.
Accordingly, what is needed in the art is a flash memory cell having greater storage ability and a long data retention time.